The present invention relates generally to rapid thermal anneal semiconductor processing equipment “(RTP equipment”), and particularly to a technique utilizing sichrome (SiCr) film material on semiconductor wafers for use in calibrating and/or monitoring the calibration of RTP equipment. The invention also relates to adjusting the sheet resistances and TCR (temperature coefficient of resistance) of sichrome film resistors in integrated circuits.
The term “RTP equipment” refers to “rapid thermal processing equipment”. (The RTP equipment is sometimes also referred to as “RTA equipment” or “rapid thermal anneal” equipment.) A typical RTP chamber includes an oven or chamber the temperature of which is rapidly increased or “ramped up” during processing of a single integrated circuit wafer from about 300 degrees Centigrade to about 1200 degrees Centigrade. The chamber temperature is maintained at that temperature for a short time (e.g., 30 seconds to 5 minutes), and then the temperature is rapidly ramped back down to a low level, the wafer then is removed, and the anneal process is performed on another integrated circuit wafer. FIG. 1 is a generalized diagram of a typical RTP chamber 1.
Referring to FIG. 1, RTP chamber 1 includes a sealed housing 2 having a door 2A through which access to the interior of housing 2 can be achieved. An upper heating element 3A including an array of tungsten lamps is located above a boat 4 on which a semiconductor wafer 5 is supported. A lower heating element 3B also including an array of tungsten lamps is located below boat 4. Typically, a gas flow inlet 14 is provided through housing 2 to maintain a suitable ambient atmosphere within housing 2, either for performing a processing step on wafer 5 (such as oxide growth) or to provide an inert ambient atmosphere during the annealing process. A control system 10 of RTP chamber 1 includes a controller or CPU 12, an analog to digital converter 11, and a digital to analog control system 13 that controls, via power bus 6, the amount of power delivered to upper and lower heating elements 3A and 3B. A permanent thermocouple or pyrometer 8 for measuring the temperature of the wafer is coupled by a conductor or bus 9 to an analog input of analog to digital converter 11. (Alternatively, a pyrometer or other permanent or semi-permanent temperature measuring device, also referred to herein by reference numeral 8, can be provided to generate a signal representing the temperature within RTP chamber 1.) CPU or microcontroller 12 reads the digital output of analog to digital converter 11 and digitally processes it to provide a digital feedback signal on conductor 6 as an input to digital to analog converter power control system 13 to cause upper and lower heating elements 3A and 3B to maintain the temperature of wafer boat 4 and wafer 5 thereon precisely at any predetermined temperature within a wide range.
The temperature in RTP chamber 1 can be rapidly ramped up to the desired anneal temperature at the rate of approximately 50 to 150 degrees Centigrade per second by means of heating elements 3A and 3B. The anneal temperature can be precisely maintained for a desired anneal duration. The temperature in RTP chamber 1 can be ramped down at the rate of 100 to 150 degrees Centigrade per second just by turning off heating elements 3A and 3B.
Annealing operations are commonly used in implant “activation” processes, in silicide formation processes, and in oxidation processes. For example, oxide growth processes may include growth of gate oxides on silicon or growth of oxides on polycrystalline silicon. The silicide processes referred to may be for forming titanium silicide, cobalt silicide, or nickel silicide in contact structures in integrated circuits.
RTP chambers of the type described above with reference to FIG. 1 are commonly used in semiconductor manufacturing facilities to perform the above-mentioned annealing applications. The above-mentioned implant “activation” of ion implanted regions previously formed on/in the surface of a silicon wafer involves annealing the silicon wafer to drive the implanted P+ or N− ions (such as boron or arsenic ions) into the silicon to a desired junction depth to thereby activate free P+ or N− carriers in the implanted region. (Specifically, the implanting of the wafer surface with boron or arsenic ions or the like, followed by a suitable to rapid anneal, drives most of the implanted species into the crystal lattice at a desired junction depth. This activates the implanted species by modifying the band gap properties of the semiconductor material thereby producing mobile charge carriers in the implanted region of semiconductor material, reducing its resistivity and sheet resistance Rs. RTP chambers are also used for performing the above-mentioned silicide processes, and also for growing thin oxides or nitrides on silicon wafers.)
The above-mentioned silicide processes are used in manufacture of typical MOS (including CMOS) structures, the manufacture of which includes forming a thin gate oxide over the region between a source electrode region and a drain electrode region in a silicon wafer, forming a doped polycrystalline silicon (“poly”) gate electrode on the gate oxide, and forming a layer of refractory metal such as titanium on the wafer. Then the wafer is placed in an RTP chamber and annealed at a particular anneal temperature for a particular anneal duration, e.g., at 600 degrees Centigrade for 30 seconds. This causes formation of titanium silicide (TiSix) in regions under the contact openings where silicon molecules are available to combine with the titanium. The titanium silicide has reduced sheet resistance and therefore provides lower contact resistance of the titanium metallization to the various MOS transistor electrodes. Often, a second annealing step is then performed at 750 degrees Centigrade, which causes formation of further formation of a stable and low resistance phase of titanium silicide TiSi2.
The above-mentioned annealing of implanted wafers and silicide formation on semiconductor wafers causes a reduction ΔRs in the sheet resistance Rs of the implanted regions or silicided regions. The reduction in sheet resistance ΔRs due to the annealing is a particular function of the anneal temperature if the anneal time is kept constant.
There are various causes of drift of the temperature in RTP chamber 1, including gradual deterioration of the lamps used as heating elements 3A and 3B and gradual deterioration of the accuracy of permanent thermocouple or pyrometer 8. Also, annealing of doped oxides in RTP chamber 1 may gradually contaminate it and cause errors in temperature measurements using permanent thermocouple or pyrometer 8.
Achieving accurate measurement and control of the temperature of RTP chamber 1 is very important in many applications because many anneal processes are very dependent on precise control of the RTP chamber anneal temperatures.
For example, in an annealing process for implant activation, the desired junction depth and sheet resistance may not be achieved if the anneal temperature is not accurately determined in the RTP chamber, even if the implant dose is correct. Also, in an annealing process used to grow silicon dioxide, the oxide thickness is likely to be unacceptably inaccurate if the annealing temperature is inaccurate. In a silicide annealing process, the silicide may propagate into the silicon and damage the crystal structure and/or result in a poor quality silicide that results in high contact resistance to electrodes of the transistors. In fact, some sub-micron semiconductor manufacturing processes cannot tolerate a variation of even as little as +−3 degrees Centigrade in the annealing temperatures in RTP chamber 1.
Known techniques for calibrating RTP chambers include use of a “thermocouple wafer”, which includes a platinum thermocouple attached to a semiconductor wafer. The thermocouple wafer has to be placed within the RTP chamber and coupled to a data recording device, which requires more technically skilled personnel than is usually required for routine operation and maintenance of an RTP chamber used in a semiconductor manufacturing process. Therefore, use of a thermocouple wafer usually necessitates the inconvenience of scheduling the services of such skilled technical personnel.
An advantage of a thermocouple wafer is that it can be utilized to accurately calibrate the permanent thermocouple or pyrometer 8 of RTP chamber 1 over its entire operating temperature range, but unfortunately, the technique of using a thermocouple wafer to calibrate the interior temperature of an RTP chamber requires the above-mentioned connecting of the thermocouple wafer to the external data recording device by the above-mentioned skilled technical personnel. This is very time-consuming, necessitating a large amount of down time of the RTP chamber, and therefore is very costly.
As an example, if the thermocouple wafer has been installed in RTP chamber 1 and the temperature therein has been ramped up to a desired anneal temperature of 900 degrees Centigrade, permanent thermocouple or pyrometer 8 may indicate that the RTP chamber temperature is only 850 degrees Centigrade but the thermocouple wafer may indicate that the actual anneal temperature is 900 degrees Centigrade. This is likely to necessitate a re-calibration of RTP chamber 1, which can be accomplished in various ways. (However, sometimes what appears to be a temperature drift error of the permanent thermocouple or pyrometer 8 of RTP chamber 1 is actually caused by drift in the ion implanter (not shown) that implanted the test wafers to be used for calibrating or checking the calibration of the RTP chamber. To determine whether or not this is the case, the usual technique of monitoring the calibration of the RTP chamber includes implanting at least two different batches of implant test wafers, and then simultaneously annealing at least a wafer from each batch in RTP chamber 1 and obtaining a match. Subsequent batches have to be matched before one batch of wafers runs out. Then, if the measured sheet resistance change ΔRs due to the annealing is not the same for implant test wafers from the different batches, then the perceived temperature drift is considered to be actually caused by the drift of the implanter rather than drift of RTP chamber 1.)
If it is determined that calibration of RTP chamber 1 is required, the calibration may be accomplished by software executed by CPU 11 to modify the feedback on bus 6 to control heating lamps 3A and 3B so as to cause the actual temperature in RTP chamber 1 to precisely match a signal value or readout value produced by or in response to permanent thermocouple or pyrometer 8. Alternatively, software may be executed by CPU 11 to modify the readout of permanent thermocouple or pyrometer 8 so it precisely matches the actual temperature in RTP chamber 1.
As described above, utilizing a thermocouple wafer to calibrate temperatures of the RTP chamber as described above is very inconvenient because the thermocouple wafer must be installed in the chamber and also connected to a data recording device. Typically, the process of checking the calibration of RTP chamber 1 using a thermocouple wafer is a tedious process that often causes approximately one-half day to a full day of RTP chamber down time, which, of course is very costly.
In the prior art, it has been found necessary to prepare batches of “implant test wafers” and/or batches of “silicide test wafers” and to frequently anneal such test wafers using RTP chamber 1 and then determine values of sheet resistance change ΔRs in order to determine when calibration of RTP chamber 1 is needed in order to maintain the needed accuracy of the annealing temperatures.
Cobalt and titanium films oxidize rapidly in the presence of oxygen gas, and therefore such test wafers must be utilized soon after they are fabricated. Furthermore, the prior RTP chamber calibration techniques using ΔRs measurements of silicide test wafers are very dependent on the properties of the semiconductor substrate and on the ambient atmosphere in the RTP chamber during annealing of the wafers therein. Specifically, the sheet resistance of suicide is a strong function of how clean the silicon substrate is. The sheet resistance of suicide is also a strong function of the amount of contamination in the RTP chamber due to contamination from other processes or atmospheric leaks.
Furthermore, accurate determination of the actual effect of contamination in the RTP chamber due to prior processes therein is difficult and tedious, and accurate evaluation of the cleanness of silicon wafers also is difficult and tedious. Nevertheless, silicide processes have been used in calibrating and monitoring the calibration of RTP chambers because accurate data for ΔRs as a function of anneal temperature and anneal duration cannot be obtained from implant test wafers for temperatures in the range between 350 degrees and 700 degrees Centigrade.
The procedure for monitoring the accuracy of the RTP chamber using an implant test wafer has been to anneal it in the RTP chamber at the desired anneal temperature for the desired amount of anneal time and then obtain the resulting sheet resistance change ΔRs. The ΔRs value is compared to previously obtained characterization data of identical implant test wafers to determine the actual RTP chamber temperature. The implant anneals are good only in the temperature range between 900 and 1200 degrees Centigrade.
Values of ΔRs based on measurements of sheet resistance of batches of implant test wafers and/or silicide test wafers annealed in RTP chamber 1 when it is accurately calibrated can be used to determine the ΔRs values, within limited temperature ranges, as a function of the RTP chamber temperature measured by permanent thermocouple or pyrometer 8. A relatively linear curve in a range from approximately 600 degrees Centigrade to approximately 750 degrees centigrade can be generated based on measurements of the titanium silicide. Similarly, a fairly linear curve of sheet resistance change ΔRs due to a particular amount of annealing vs. the RTP chamber temperature in the range from approximately 900 degrees Centigrade to 1200 degrees Centigrade can be generated from measurements of sheet resistance of implanted wafers for certain implanted species. The linearity helps in calibrating the system for any temperature within the range and to some extent allows accurate extrapolation of temperatures beyond the actual data points.
In the prior art, however, accurate data points cannot be readily obtained based on sheet resistance measurements of either implanted test wafers or silicide test wafers for temperatures between about 700 degrees Centigrade and 900 degrees Centigrade. In this range, it is always necessary to undergo the time consuming and tedious effort of utilizing a thermocouple wafer to calibrate the RTP. This information can be used later to check whether it is necessary to calibrate RTP chamber 1 and also to calibrate it if necessary.
Thus, there is an unmet need for a method of providing improved accuracy in the calibration of RTP equipment.
There also is an unmet need for a method of providing improved accuracy in the calibration of RTP equipment and also avoiding the cost and time required for utilization of thermocouple wafers in the calibration.
There also is an unmet need for a method of providing improved accuracy in the calibration of RTP equipment and also avoiding the need to utilize highly trained technical personnel in performing the calibration.
There also is an unmet need for a method of avoiding long RTP chamber down time that previously has been required in order to calibrate RTP chambers and/or monitor the calibration thereof.
There also is an unmet need for a method of avoiding the need to use implant test wafers and/or silicide test wafers to calibrate an RTP chamber and/or monitor the calibration thereof.
There also is an unmet need for a method of providing more accurate control of anneal temperatures in an RTP chamber independently of substrate and ambient effects.
There also is an unmet need for a method of making an integrated circuit including a thin film resistor of improved accuracy and which nevertheless is less costly than prior thin film resistors.